Revision 1.12 - Novenber 20, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Table 17. I/O Specifications—All CPU Speeds (Sheet 2 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
Hold Time
IOH
IOL
(min)
(TIS min)
(TIH min)
(TOV max)
(TOH min)
(min)
System Interface
GPIO00:10
GPIO11:15
GPIO16:27
GPIO28
GPIO29:31
Halt
SysErr
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
11.08
5.51
11.08
15.75
11.08
na
7.37
7.23
7.37
10.46
7.37
na
5.51
5.51
7.23
7.23
SysReset
Table 18. I/O Specifications—333 MHz to 600 MHz CPU
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
Hold Time
IOH
IOL
(minimum)
(TIS min)
(TIH min)
(TOV max)
(TOH min)
(minimum)
External Peripheral Interface (not SDRAM or PCI-E)
PerAddr05:31
PerCS0:3
PerData00:31
PerDataPar0:3
PerOE
PerReady
PerRW
PerWBE0:3
PerBLast
PerErr
ExtReset
BusReq
HoldReq
HoldAck
ExtAck
ExtReq
1.8
1
5.3
5.2
5.3
5.3
5.2
1
1
1
1
1
11.08
11.08
11.08
11.08
11.08
na
11.08
11.08
11.08
11.08
11.08
11.08
na
11.08
11.08
na
11.08
11.08
11.08
11.08
na
7.37
7.37
7.37
7.37
7.37
na
7.37
7.37
7.37
7.37
7.37
7.37
na
7.37
7.37
na
7.37
7.37
7.37
7.37
na
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
2.7
1.9
1
1
2
1
1
1
1
1
1.8
1.7
2
5.3
5.1
5
5.3
5.3
5.1
5.2
5.2
5
5.3
5.3
5.3
5.3
5.3
1
1
1
1
1
1
1
1
1
1.9
2.3
2
1
1
2.3
2
1
1
NFALE
NFCE0:3
NFCLE
NFData0:15
NFRdyBusy
NFREn
1
1
1
1
2.3
1.7
1
1
5.3
5.3
1
1
11.08
11.08
7.37
7.37
NFWEn
58
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
