Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Operation Registers
Data Sheet
Table 31. Reset Control Register
Bit
Description
31:29
nvRAM Access Control. This field provides a method for access to the optional external non-volatile memory.
Write operations are achieved by a sequence of byte operations involving these bits and the 8-bit field of bits 23
through 16. The sequence requires that the low-order address, high-order address, and then a data byte are
loaded in order. Bit 31 of this field acts as a combined enable and ready for the access to the external memory.
D31 must be written to a 1 before an access can begin, and subsequent accesses must wait for bit D31 to
become 0 (ready).
D31 D30 D29 W/R
0
1
1
1
1
0
1
X
0
0
1
1
X
X
X
0
1
0
1
X
X
W
W
W
W
W
R
Inactive
Load low address byte
Load high address byte
Begin write
Begin read
Ready
R
Busy
Cautionary note: The nonvolatile memory interface is also available for access by the Add-On interface. While
simultaneous accesses to the nv memory by both the Add-On and PCI are supported (via arbitration logic), soft-
ware must be designed to prevent the possibility of data corruption within the memory and to provide for accu-
rate data retrieval.
28
27
nvRAM Access Failed. Indicate the last nvRAM access failed. This flag is cleared automatically upon the start of
the next read/write operation.
Mailbox Flag Reset. Writing a one to this bit causes all mailbox status flags to become reset (EMPTY). It is not
necessary to write this bit to 0 afterwards because it is used internally to produce a reset pulse. Since reading
this bit will always return a 0, this bit is write only.
26
25
Reserved. Always zero.
Read FIFO Reset. Writing a one to this bit causes the read FIFO to reset (empty). It is not necessary to write a 0
to this bit. This bit is write only. This feature is intended for test only. However, it can be used during operation if
several PCI idle cycles are inserted following the assertion of this command.
24
Add-On Pin Reset. Writing a one to this bit causes the reset output pin to become active (SYSRST#). Clearing
this bit is necessary in order to remove the assertion of reset. This bit is read/write.
23:16
Non-volatile Memory Address/Data Port. This 8-bit field is used in conjunction with bits 31, 30 and 29 of this reg-
ister to access the external non-volatile memory. The contents written are either low address, high address, or
data as defined by bits 30 and 29. This register will contain the external non-volatile memory data when the
proper read sequence for bits 31 through 29 is performed.
15:0
Reserved. Always zero.
66
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