Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Operation Registers
Data Sheet
Add-On Incoming Mailbox Register (AIMB)
This DWORD register provides a method for receiving user-defined status or
parameter data from the PCI system. Add-On bus read operations to this register
may be of any width (byte, word, or DWORD). Only read operations are sup-
ported. Reading from this register can optionally cause a PCI bus interrupt (if
desired) by enabling interrupt generation through the use of the PCI’s Interrupt
Control/Status Register. This register is also referred to as the PCI Outgoing Mail-
box Register.
Incoming Mailbox
0Ch
Register Names:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
XXXXXXXXh
Read Only
32 bits
Add-On Outgoing Mailbox Register (AOMB)
This DWORD register provides a method for sending command or parameter
Outgoing Mailbox
1Ch
Register Names:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
data to the PCI interface. Add-On bus operations to this register may be of any
width (byte, word, or DWORD). Writing to this register can be a source for PCI
bus interrupts (if desired) by enabling interrupt generation through the use of the
PCI’s Interrupt Control/Status Register. This is also called the PCI Incoming Mail-
box Register (IMB). Byte 3 of this mailbox can also be controlled via the external
mailbox port. Reading from this register will not affect interrupts or the AMBEF
Status Register. (OMB).
XXXXXXXXh
Read/Write
32 bits
Add-On Pass-Thru Address Register (APTA)
This register stores the address of any active Pass-Thru PCI bus cycle
that has been accepted by the S5320. When one of the base address
decode registers 1-4 encounters a PCI bus cycle which selects the
region defined by it, this register stores that current cycle’s active
address. This address is incremented after every 32-bit Pass-Thru data
transfer.
Add-On Pass-Thru Address
Register Name:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
28h
XXXXXXXXh
Read Only
32 bits
Add-On Pass-Thru Data Register (APTD)
This register, along with APTA register, is used to perform Pass-Thru trans-
fers. When one of the base address decode registers 1-4 encounters a PCI
bus cycle which selects the region defined by it, the APTA register will con-
tain that current cycle’s active address and the APTD will contain the data
(PCI bus writes) or must be written with data (PCI bus reads). Wait states
are generated on the PCI bus until this register is read (PCI bus writes) or
this register is written (PCI bus reads) when in Passive mode.
Add-On Pass-Thru Data
2Ch
Register Name:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
XXXXXXXXh
Read/Write
32 bits
70
DS1656
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
