Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Operation Registers
ADD-ON BUS OPERATION REGISTERS
Data Sheet
This register group represents the primary method for
communication between the Add-On and PCI buses
as viewed by the Add-On. The flexibility of this
arrangement allows a number of user-defined soft-
ware protocols to be built. One should NOT read/write
from any undefined address, or the read results and
write effects cannot be guaranteed. Table 33 lists the
Add-On Bus Operation Registers.
The Add-On bus interface provides access to 8
DWORDs of data, control and status information. All of
these locations are accessed by asserting the Add-On
bus chip select pin (SELECT#) and the byte-enable
pins (BE[3:0]), in conjunction with either the read or
write control enables (signal pin RD# or WR#). All reg-
isters are accessed with signals synchronous to the
Add-On clock.
Table 33. Operation Registers - Add-On Interface
Address
0Ch
1Ch
28h
Abbreviation
AIMB
Register Name
Add-On Incoming Mailbox Register
AOMB
APTA
Add-On Outgoing Mailbox Register
Add-On Pass-Thru Address Register
Add-On Pass-Thru Data Register
2Ch
34h
APTD
AMBEF
AINT
Add-On Mailbox Empty/Full Status Register
Add-On Interrupt Control/Status Register
Add-On Reset Control Register
38h
3Ch
60h
ARCR
APTCR
Add-On Pass-Thru Configuration Register
AMCC Confidential and Proprietary
DS1656
69
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
