Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
Maximum Latency Register (MAXLAT)
This register may be optionally used by bus masters to
specify how often this device needs PCI bus access. A
value of zero indicates that the bus master has no
stringent requirement. The units defined by the least
significant bit are in 250 ns increments. Since the
S5320 is a PCI target device only, this register is
treated as “information only” and has no further imple-
mentation within this device.
Maximum Latency
3Fh
Register Name:
Address Offset:
Power-up value:
Boot-load:
00h, hardwired
not used
Read Only
8 bits
Attribute:
Size:
Figure 24. Maximum Latency Register
Bit
7
0
Value
00h
AMCC Confidential and Proprietary
DS1656
57
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
