Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
Table 27. Read Response to Expansion ROM Base Address Register (after all ones written)
Response
00000000h
FFFFF801h
Size in Bytes
none - disabled
nvRAM boot value
00000000h or BIOS missing 1
FFFFF801h
2K bytes (512 DWORDs)
1. The Expansion ROM Base Address Register nvRAM boot value is internally hardwired to FFFFF80Xh, where X = 000xb (i.e., only the least-
significant bit, or Address Decode Enable bit, is programmable). This defines both the minimum and maximum expansion ROM size sup-
ported by the S5320 (2K bytes). The Address Decode Enable bit in the nvRAM (the LSB) must be set to enable this region. If not set, a PCI
Configuration read of this region will always respond with 00000000h.
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