Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Operation Registers
OPERATION REGISTERS
Data Sheet
PCI BUS OPERATION REGISTERS
All S5320 control and communications are performed
through two register groups: PCI Operation Registers
Add-On Operation Registers. Some registers in both
groups are accessible from both buses. This chapter
describes the PCI Operation Register set first and then
the Add-On Operation Register set for easier under-
standing. An access to a register common to both
buses at the same time is not allowed. Unpredictable
behavior may occur.
The PCI bus operation registers are mapped as 6
DWORD registers located at the address space (I/O or
memory) specified by Base Address Register 0. These
locations are the primary method of communication
between the PCI and Add-On buses. It is NOT recom-
mended to read or write from an undefined address.
The read results and write effects cannot be guaran-
teed. Table 28 lists the PCI Bus Operation Registers.
Table 28. Operation Registers - PCI Bus
Address Offset
Abbreviation
OMB
Register Name
Outgoing Mailbox Register
0Ch
1Ch
34h
38h
3Ch
60h
IMB
Incoming Mailbox Register
MBEF
Mailbox Empty/Full Status Register
Interrupt Control/Status Register
Reset Control Register
INTCSR
RCR
PTCR
Pass-Thru Configuration Register
Note: Absolute register address locations are acquired by adding BADR0 to the “address offset” listed above.
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