Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
Cache Line Size Register (CALN)
The cache line configuration register is used by bus
masters implementing memory write and invalidate
commands. The register defines the cache line size in
double word (64-bit) increments. The S5320 is a target
device not requiring cache. The register is hardwired
to 0.
Cache Line Size
0Ch
Register Name:
Address Offset:
Power-up value:
Boot-load:
00h, hardwired
not used
Read Only
8 bits
Attribute:
Size:
Figure 12. Cache Line Size Register
7
0
00h
Cache Line Size (RO)
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