MAX 7000A Programmable Logic Device Data Sheet
The programming times described in Tables 5 through 7 are associated
with the worst-case method using the enhanced ISP algorithm.
Table 5. MAX 7000A tPULSE & CycleTCK Values
Device
Programming
Stand-Alone Verification
tVPULSE (s) CycleVTCK
t
PPULSE (s)
CyclePTCK
EPM7032AE
EPM7064AE
EPM7128AE
EPM7256AE
EPM7512AE
EPM7128A (1)
EPM7256A (1)
2.00
2.00
2.00
2.00
2.00
5.11
6.43
55,000
105,000
205,000
447,000
890,000
832,000
1,603,000
0.002
0.002
0.002
0.002
0.002
0.03
18,000
35,000
68,000
149,000
297,000
528,000
1,024,000
0.03
Tables 6 and 7 show the in-system programming and stand alone
verification times for several common test clock frequencies.
Table 6. MAX 7000A In-System Programming Times for Different Test Clock Frequencies
Device
fTCK
Units
10 MHz 5 MHz
2 MHz
1 MHz 500 kHz 200 kHz 100 kHz 50 kHz
EPM7032AE
EPM7064AE
EPM7128AE
EPM7256AE
EPM7512AE
EPM7128A (1)
EPM7256A (1)
2.01
2.01
2.02
2.05
2.09
5.19
6.59
2.01
2.02
2.04
2.09
2.18
5.27
6.75
2.03
2.05
2.10
2.23
2.45
5.52
7.23
2.06
2.11
2.21
2.45
2.89
5.94
8.03
2.11
2.21
2.41
2.90
3.78
6.77
9.64
2.28
2.53
3.03
4.24
6.45
9.27
14.45
2.55
3.05
3.10
4.10
s
s
s
s
s
s
s
4.05
6.10
6.47
10.94
19.80
21.75
38.49
10.90
13.43
22.46
Altera Corporation
19
ALTERA [ ALTERA CORPORATION ]
