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EPM7256AEFC256-5 参数 Datasheet PDF下载

EPM7256AEFC256-5图片预览
型号: EPM7256AEFC256-5
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 5.5ns, 256-Cell, CMOS, PBGA256, FINE LINE, BGA-256]
分类和应用: 时钟LTE输入元件可编程逻辑
文件页数/大小: 64 页 / 437 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 7000A Programmable Logic Device Data Sheet  
The instruction register length of MAX 7000A devices is 10 bits. The user  
electronic signature (UES) register length in MAX 7000A devices is 16 bits.  
The MAX 7000AE USERCODE register length is 32 bits. Tables 9 and 10  
show the boundary-scan register length and device IDCODE information  
for MAX 7000A devices.  
Table 9. MAX 7000A Boundary-Scan Register Length  
Device  
Boundary-Scan Register Length  
EPM7032AE  
EPM7064AE  
EPM7128A  
EPM7128AE  
EPM7256A  
EPM7256AE  
EPM7512AE  
96  
192  
288  
288  
480  
480  
624  
Table 10. 32-Bit MAX 7000A Device IDCODE Note (1)  
Device  
IDCODE (32 Bits)  
Version  
(4 Bits)  
Part Number (16 Bits) Manufacturer’s 1 (1 Bit)  
Identity (11 Bits)  
(2)  
EPM7032AE  
EPM7064AE  
EPM7128A  
EPM7128AE  
EPM7256A  
EPM7256AE  
EPM7512AE  
0001  
0001  
0000  
0001  
0000  
0001  
0001  
0111 0000 0011 0010 00001101110  
0111 0000 0110 0100 00001101110  
0111 0001 0010 1000 00001101110  
0111 0001 0010 1000 00001101110  
0111 0010 0101 0110 00001101110  
0111 0010 0101 0110 00001101110  
0111 0101 0001 0010 00001101110  
1
1
1
1
1
1
1
Notes:  
(1) The most significant bit (MSB) is on the left.  
(2) The least significant bit (LSB) for all JTAG IDCODEs is 1.  
See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera  
Devices) for more information on JTAG BST.  
f
22  
Altera Corporation  
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