MAX 7000A Programmable Logic Device Data Sheet
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
■
■
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (TCK) frequency and the
number of TCKcycles to shift instructions, address, and data into the
device.
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000A Device
The time required to program a single MAX 7000A device in-system can
be calculated from the following formula:
Cycle
PTCK
t
= t
+ -------------------------------
PROG
PPULSE
f
TCK
where: tPROG
= Programming time
= Sum of the fixed times to erase, program, and
verify the EEPROM cells
tPPULSE
CyclePTCK = Number of TCKcycles to program a device
fTCK = TCKfrequency
The ISP times for a stand-alone verification of a single MAX 7000A device
can be calculated from the following formula:
Cycle
VTCK
t
= t
+ --------------------------------
VER
VPULSE
f
TCK
where: tVER
tVPULSE
CycleVTCK = Number of TCKcycles to verify a device
= Verify time
= Sum of the fixed times to verify the EEPROM cells
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Altera Corporation
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