MAX 7000 Programmable Logic Device Family Data Sheet
Table 26. MAX 7000 & MAX 7000E Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-15T
Min Max Min Max Min Max
Unit
-15
-20
t
t
t
t
t
t
t
t
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
2.0
2.0
–
3.0
3.0
4.0
9.0
2.0
8.0
8.0
4.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IO
(2)
(2)
FIN
Shared expander delay
Parallel expander delay
Logic array delay
10.0
1.0
6.0
6.0
–
SEXP
PEXP
LAD
LAC
IOE
OD1
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Slow slew rate = off
C1 = 35 pF
4.0
V
= 5.0 V
CCIO
t
t
t
t
t
Output buffer and pad delay
Slow slew rate = off
C1 = 35 pF (7)
C1 = 35 pF (2)
C1 = 35 pF
5.0
8.0
6.0
–
–
6.0
9.0
ns
ns
ns
ns
ns
OD2
OD3
ZX1
ZX2
ZX3
V
= 3.3 V
CCIO
Output buffer and pad delay
Slow slew rate = on
V
= 5.0 V or 3.3 V
CCIO
Output buffer enable delay
Slow slew rate = off
6.0
–
10.0
11.0
14.0
10.0
V
= 5.0 V
CCIO
Output buffer enable delay
Slow slew rate = off
C1 = 35 pF (7)
C1 = 35 pF (2)
C1 = 5 pF
7.0
10.0
6.0
V
= 3.3 V
CCIO
Output buffer enable delay
Slow slew rate = on
–
V
= 5.0 V or 3.3 V
CCIO
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output buffer disable delay
Register setup time
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XZ
4.0
4.0
2.0
2.0
4.0
4.0
–
4.0
5.0
4.0
3.0
SU
Register hold time
H
Register setup time of fast input (2)
Register hold time of fast input (2)
Register delay
FSU
FH
–
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
13.0
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
15.0
1.0
1.0
8.0
8.0
3.0
4.0
4.0
3.0
15.0
RD
Combinatorial delay
Array clock delay
COMB
IC
Register enable time
Global control delay
Register preset time
Register clear time
EN
GLOB
PRE
CLR
PIA
LPA
PIA delay
Low-power adder
(8)
38
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
