MAX 7000 Programmable Logic Device Family Data Sheet
Table 25. MAX 7000 & MAX 7000E External Timing Parameters
Symbol Parameter Conditions
Note (1)
Speed Grade
-15T
Min Max Min Max Min Max
Unit
-15
-20
t
t
Input to non-registered output C1 = 35 pF
15.0
15.0
15.0
15.0
20.0
20.0
ns
ns
PD1
PD2
I/O input to non-registered
output
C1 = 35 pF
t
t
t
Global clock setup time
Global clock hold time
11.0
0.0
11.0
0.0
–
12.0
0.0
ns
ns
ns
SU
H
Global clock setup time of fast (2)
3.0
5.0
FSU
input
t
Global clock hold time of fast
input
(2)
0.0
–
0.0
ns
FH
t
t
t
t
t
t
t
t
t
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
C1 = 35 pF
8.0
8.0
12.0
20.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
CO1
CH
5.0
5.0
4.0
4.0
6.0
6.0
4.0
4.0
6.0
6.0
5.0
5.0
CL
ASU
AH
C1 = 35 pF
15.0
15.0
ACO1
ACH
ACL
CPPW
6.0
6.0
6.0
6.5
6.5
6.5
8.0
8.0
8.0
Minimum pulse width for clear (3)
and preset
t
Output data hold time after
clock
C1 = 35 pF (4)
1.0
1.0
1.0
ns
ODH
t
f
Minimum global clock period
13.0
13.0
13.0
13.0
16.0
16.0
ns
CNT
CNT
Maximum internal global clock (5)
frequency
76.9
76.9
62.5
MHz
t
f
Minimum array clock period
ns
ACNT
ACNT
Maximum internal array clock (5)
frequency
76.9
100
76.9
83.3
62.5
83.3
MHz
f
Maximum clock frequency
(6)
MHz
MAX
Altera Corporation
37
ALTERA [ ALTERA CORPORATION ]
