MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000 architecture supports 100% TTL emulation and
high-density integration of SSI, MSI, and LSI logic functions. The
MAX 7000 architecture easily integrates multiple devices ranging from
PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices
are available in a wide range of packages, including PLCC, PGA, PQFP,
RQFP, and TQFP packages. See
Table 5. MAX 7000 Maximum User I/O Pins
Device
160-
Pin
PQFP
160-
Pin
PGA
192-
Pin
PGA
208-
Pin
PQFP
208-
Pin
RQFP
44-
44-
44-
68-
84- 100- 100-
Pin
Pin
Pin
Pin
Pin
Pin
Pin
PLCC PQFP TQFP PLCC PLCC PQFP TQFP
36
36
36
36
36
36
36
36
36
52
52
68
68
64
68
68
64
64
76
84
84
84
84
84
68
68
EPM7032
EPM7032S
EPM7064
EPM7064S
EPM7096
EPM7128E
EPM7128S
EPM7160E
EPM7160S
EPM7192E
EPM7192S
EPM7256E
EPM7256S
Notes:
(1)
(2)
100
100
104
104
124
124
132
164
164
164
164
124
When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins
become JTAG pins.
Perform a complete thermal analysis before committing a design to this device package. For more information, see
the
MAX 7000 devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000 architecture accommodates a
variety of independent combinatorial and sequential logic functions. The
devices can be reprogrammed for quick and efficient iterations during
design development and debug cycles, and can be programmed and
erased up to 100 times.
Altera Corporation
5
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