MAX 7000 Programmable Logic Device Family Data Sheet
■
■
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, and VeriBest
Programming support
–
Altera’s Master Programming Unit (MPU) and programming
hardware from third-party manufacturers program all
MAX 7000 devices
–
The BitBlaster
TM
serial download cable, ByteBlasterMV
TM
parallel port download cable, and MasterBlaster
TM
serial/universal serial bus (USB) download cable program MAX
7000S devices
General
Description
The MAX 7000 family of high-density, high-performance PLDs is based
on Altera’s second-generation MAX architecture. Fabricated with
advanced CMOS technology, the EEPROM-based MAX 7000 family
provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns,
and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6,
-7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in
-5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
Group (PCI SIG)
PCI Local Bus Specification, Revision 2.2.
See
for available speed grades.
Table 3. MAX 7000 Speed Grades
Device
-5
EPM7032
EPM7032S
EPM7064
EPM7064S
EPM7096
EPM7128E
EPM7128S
EPM7160E
EPM7160S
EPM7192E
EPM7192S
EPM7256E
EPM7256S
Speed Grade
-6
v
v
v
v
v
v
-7
v
v
v
v
v
v
v
v
v
v
v
v
v
v
-10P
-10
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
-12P
-12
v
-15
v
-15T
v
-20
Altera Corporation
3
ALTERA [ ALTERA CORPORATION ]
