MAX 3000A Programmable Logic Device Family Data Sheet
The programming times described in
through
are associated
with the worst-case method using the enhanced ISP algorithm.
Table 4. MAX 3000A t
PULSE
& Cycle
TCK
Values
Device
Programming
t
PPULSE
(s)
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
2.00
2.00
2.00
2.00
2.00
Stand-Alone Verification
t
VPULSE
(s)
0.002
0.002
0.002
0.002
0.002
Cycle
PTCK
55,000
105,000
205,000
447,000
890,000
Cycle
VTCK
18,000
35,000
68,000
149,000
297,000
and
6
show the in-system programming and stand alone
verification times for several common test clock frequencies.
Table 5. MAX 3000A In-System Programming Times for Different Test Clock Frequencies
Device
10 MHz
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
2.01
2.01
2.02
2.05
2.09
f
TCK
5 MHz
2.01
2.02
2.04
2.09
2.18
Units
200 kHz
2.28
2.53
3.03
4.24
6.45
2 MHz
2.03
2.05
2.10
2.23
2.45
1 MHz
2.06
2.11
2.21
2.45
2.89
500 kHz
2.11
2.21
2.41
2.90
3.78
100 kHz
2.55
3.05
4.05
6.47
10.90
50 kHz
3.10
4.10
6.10
10.94
19.80
s
s
s
s
s
Table 6. MAX 3000A Stand-Alone Verification Times for Different Test Clock Frequencies
Device
10 MHz
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
0.00
0.01
0.01
0.02
0.03
f
TCK
5 MHz
0.01
0.01
0.02
0.03
0.06
Units
200 kHz
0.09
0.18
0.34
0.75
1.49
2 MHz
0.01
0.02
0.04
0.08
0.15
1 MHz
0.02
0.04
0.07
0.15
0.30
500 kHz
0.04
0.07
0.14
0.30
0.60
100 kHz
0.18
0.35
0.68
1.49
2.97
50 kHz
0.36
0.70
1.36
2.98
5.94
s
s
s
s
s
16
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
