MAX 3000A Programmable Logic Device Family Data Sheet
Figure 7 shows the timing information for the JTAG signals.
Figure 7. MAX 3000A JTAG Waveforms
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to Be
Captured
tJSCO
tJSZX
tJSXZ
Signal
to Be
Driven
Table 10 shows the JTAG timing parameters and values for MAX 3000A
devices.
Table 10. JTAG Timing Parameters & Values for MAX 3000A Devices
Symbol
Parameter
Min Max Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
TCKclock period
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
JCP
TCKclock high time
TCKclock low time
JTAG port setup time
JTAG port hold time
JCH
50
JCL
20
45
JPSU
JPH
JTAG port clock to output
25
25
25
JPCO
JPZX
JPXZ
JSSU
JSH
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
20
45
Capture register hold time
Update register clock to output
25
25
25
JSCO
JSZX
JSXZ
Update register high impedance to valid output
Update register valid output to high impedance
Altera Corporation
19
ALTERA [ ALTERA CORPORATION ]
