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EPM240T100C5 参数 Datasheet PDF下载

EPM240T100C5图片预览
型号: EPM240T100C5
PDF下载: 下载PDF文件 查看货源
内容描述: [最大II器件]
分类和应用: 可编程逻辑器件输入元件PC
文件页数/大小: 295 页 / 3815 K
品牌: ALTERA [ ALTERA CORPORATION ]
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13. IEEE 1149.1 (JTAG) Boundary-Scan  
Testing for MAX II Devices  
MII51014-1.7  
Introduction  
As printed circuit boards (PCBs) become more complex, the need for thorough testing  
becomes increasingly important. Advances in surface-mount packaging and PCB  
manufacturing have resulted in smaller boards, making traditional test methods (for  
example, external test probes and “bed-of-nails” test fixtures) harder to implement.  
As a result, cost savings from PCB space reductions are sometimes offset by cost  
increases in traditional testing methods.  
In the 1980s, the Joint Test Action Group (JTAG) developed a specification for  
boundary-scan testing that was later standardized as the IEEE Std. 1149.1  
specification. This boundary-scan test (BST) architecture offers the capability to  
efficiently test components on PCBs with tight lead spacing.  
This BST architecture can test pin connections without using physical test probes and  
capture functional data while a device is operating normally. Boundary-scan cells in a  
device can force signals onto pins, or capture data from pin or core logic signals.  
Forced test data is serially shifted into the boundary-scan cells. Captured data is  
serially shifted out and externally compared to expected results. Figure 13–1 shows  
the concept of boundary-scan testing.  
Figure 13–1. IEEE Std. 1149.1 Boundary-Scan Testing  
Boundary-Scan Cell  
Serial  
Data In  
Serial  
Data Out  
IC Pin Signal  
Core  
Logic  
Core  
Logic  
Interconnection  
to Be Tested  
JTAG Device 1  
JTAG Device 2  
®
This chapter discusses how to use the IEEE Std. 1149.1 BST circuitry in MAX II  
devices. The topics are as follows:  
“IEEE Std. 1149.1 BST Architecture” on page 13–2  
“IEEE Std. 1149.1 Boundary-Scan Register” on page 13–3  
“IEEE Std. 1149.1 BST Operation Control” on page 13–6  
“I/O Voltage Support in JTAG Chain” on page 13–15  
“BST for Programmed Devices” on page 13–15  
“Disabling IEEE Std. 1149.1 BST Circuitry” on page 13–16  
“Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing” on page 13–16  
“Boundary-Scan Description Language (BSDL) Support” on page 13–17  
© October 2008 Altera Corporation  
MAX II Device Handbook  
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