9–6
Chapter 9: Using User Flash Memory in MAX II Devices
UFM Functional Description
Figure 9–3. UFM Data Register
MAX II UFM Block
Data Register
16
16
DRDin
DRDout
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DRCLK
MSB
LSB
UFM Program/Erase Control Block
The UFM program/erase control block is used to generate all the control signals
necessary to program and erase the UFM block independently. This reduces the
number of LEs necessary to implement a UFM controller in the logic array. It also
guarantees correct timing of the control signals to the UFM. A rising edge on either
PROGRAMor ERASEcauses this control signal block to activate and begin sequencing
through the program or erase cycle. At this point, for a program instruction, whatever
data is in the data register will be written to the address pointed to by the address
register.
Only sector erase is supported by the UFM. Once an ERASEcommand is executed,
this control block will erase the sector whose address is stored in the address register.
When the PROGRAMor ERASEcommand first activates the program/erase control
block, the BUSYsignal will be driven high to indicate an operation in progress in the
UFM. Once the program or erase algorithm is completed, the BUSYsignal will be
forced low.
Oscillator
OSC_ENA, one of the input signals in the UFM block, is used to enable the oscillator
signal to output through the OSCoutput port. You can use this OSCoutput port to
connect with the interface logic in the logic array. It can be routed through the logic
array and fed back as an input clock for the address register (ARCLK) and the data
register (DRCLK). The output frequency of the OSCport is one-fourth that of the
oscillator frequency. As a result, the frequency range of the OSCport is 3.3 to 5.5 MHz.
The maximum clock frequency accepted by ARCLKand DRCLKis 10 MHz and the
duty cycle accepted by the DRCLKand ARCLKinput ports is approximately 45% to
50%.
When the OSC_ENAinput signal is asserted, the oscillator is enabled and the output is
routed to the logic array through the OSCoutput. When the OSC_ENAis set low, the
OSCoutput drives constant low. The routing delay from the OSCport of the UFM
block to OSCoutput pin depends on placement. You can analyze this delay using the
Quartus II timing analyzer.
MAX II Device Handbook
© October 2008 Altera Corporation
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