8–4
Chapter 8: Using MAX II Devices in Multi-Voltage Systems
5.0-V Device Compatibility
Figure 8–3. MAX II Device Compatibility with 5.0-V CMOS Devices
5.0 V 0.5 V
3.3 V
V
V
CCIO
CCIO
V
CCIO
(1)
REXT
Open Drain
VOUT
Model as RINT
5.0-V CMOS
Device
A
VIN
VSS
Note to Figure 8–3:
(1) This diode is only active after power-up. MAX II devices require an external diode if driven by 5.0 V before power-up.
The open-drain pin never drives high, only low or tri-state. When the open-drain pin
is active, it drives low. When the open-drain pin is inactive, the pin is tri-stated and
the trace pulls up to 5.0 V by the external resistor. The purpose of enabling the I/O
clamp diode is to protect the MAX II device’s I/O pins. The 3.3-V VCCIO supplied to the
I/O clamp diodes causes the voltage at point A to clamp at 4.0 V, which meets the
MAX II device’s reliability limits when the trace voltage exceeds 4.0 V. The device
operates successfully because a 5.0-V input is within its input specification.
1
The I/O clamp diode is only supported in the EPM1270 and EPM2210 devices’ I/O
Bank 3. An external protection diode is needed for other I/O banks in EPM1270 and
EPM2210 devices and all I/O pins in EPM240 and EPM570 devices.
The pull-up resistor value should be small enough for sufficient signal rise time, but
large enough so that it does not violate the IOL (output low) specification of MAX II
devices.
The maximum MAX II device IOL depends on the programmable drive strength of the
I/O output. Table 8–1 shows the programmable drive strength settings that are
available for the 3.3-V LVTTL/LVCMOS I/O standard for MAX II devices. The
Quartus II software uses the maximum current strength as the default setting. The PCI
I/O standard is always set at 20 mA with no alternate setting.
Table 8–1. 3.3-V LVTTL/LVCMOS Programmable Drive Strength
I/O Standard
3.3-V LVTTL
IOH/IOL Current Strength Setting (mA)
16
8
3.3-V LVCMOS
8
4
MAX II Device Handbook
© October 2008 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
