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EPM240T100C5 参数 Datasheet PDF下载

EPM240T100C5图片预览
型号: EPM240T100C5
PDF下载: 下载PDF文件 查看货源
内容描述: [最大II器件]
分类和应用: 可编程逻辑器件输入元件PC
文件页数/大小: 295 页 / 3815 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 8: Using MAX II Devices in Multi-Voltage Systems  
8–3  
MultiVolt Core and I/O Operation  
MultiVolt Core and I/O Operation  
MAX II devices include MultiVolt core I/O operation capability, allowing the core and  
I/O blocks of the device to be powered-up with separate supply voltages. The  
VCCINTpins supply power to the device core and the VCCIOpins supply power to  
the device I/O buffers. The VCCINTpins can be powered-up with 1.8 V for MAX IIG  
and MAX IIZ devices or 2.5/3.3 V for MAX II devices. All the VCCIOpins for a given  
I/O bank that have MultiVolt capability should be supplied from the same voltage  
level (for example, 5.0, 3.3, 2.5, 1.8, or 1.5 V). See Figure 8–2.  
Figure 8–2. Implementing a Multiple-Voltage System with a MAX II Device (Note 1), (2), (3), (4)  
1.8 V/2.5 V/3.3 V  
Power Supply  
V
CCINT  
V
CCIO  
V
CCIO  
5.0-V  
MAX II  
3.3-V  
Device  
Device  
Device  
V
CCIO  
2.5-V  
Device  
Notes to Figure 8–2:  
(1) For MAX IIG and MAX IIZ devices, VCCINTpins will only accept a 1.8-V power supply.  
(2) For MAX II devices, VCCINTpins will only accept a 2.5-V or 3.3-V power supply.  
(3) MAX II devices can drive a 5.0-V TTL input when VCCIO = 3.3 V. To drive a 5.0-V CMOS, an open-drain setting with  
internal I/O clamp diode and external resistor are required.  
(4) MAX II devices can be 5.0-V tolerant with the use of an external resistor and the internal I/O clamp diode on EPM1270  
and EPM2210 devices.  
5.0-V Device Compatibility  
A MAX II device can drive a 5.0-V TTL device by connecting the VCCIO pins of the  
MAX II device to 3.3 V. This is possible because the output high voltage (VOH) of a 3.3-  
V interface meets the minimum high-level voltage of 2.4 V of a 5.0-V TTL device.  
A MAX II device may not correctly interoperate with a 5.0-V CMOS device if the  
output of the MAX II device is connected directly to the input of the 5.0-V CMOS  
device. If the MAX II device‘s VOUT is greater than VCCIO, the PMOS pull-up transistor  
still conducts if the pin is driving high, preventing an external pull-up resistor from  
pulling the signal to 5.0 V. To make MAX II device outputs compatible with 5.0-V  
CMOS devices, configure the output pins as open-drain pins with the I/O clamp  
diode enabled, and use an external pull-up resistor. See Figure 8–3.  
© October 2008 Altera Corporation  
MAX II Device Handbook  
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