Chapter 14: Using Jam STAPL for ISP via an Embedded Processor
Embedded Systems
14–3
Figure 14–2.
Interface Logic Design Example
data[1..0][2..0]
result[2..0]
Byteblaster_nProcessor_Select
PR
D
Q
TDI_Reg
LPM_MUX
ByteBlaster_nProcessor_Select
ByteBlaster_TDI
DATA3
ByteBlaster_TMS
ByteBlaster_TCK
ByteBlaster_TDO
TDO
EN
CLR
ByteBlaster_TDI
TDI_Reg
PR
D
Q
ByteBlaster_TMS
TMS_Reg
TMS_Reg
ByteBlaster_TCK
TCK_Reg
DATA2
data[1][1]
data[0][2]
data[1][2]
data[0][0]
data[1][0]
data[0][1]
EN
CLR
PR
D
address_decode
adr[19..0]
adr[19..0] AD_VALID
DATA1
Q
TCK_Reg
EN
CLR
result0
result1
TDI
TMS
TCK
nDS
result2
d[3..0]
R_nW
R_AS
CLK
nRESET
DATA0
TDO
In
the embedded processor asserts the JTAG chain’s address, and the
R_nW
and
R_AS
signals can be set to tell the interface PLD when the processor wants
to access the chain. A write involves connecting the data path
data[3..0]
to the
JTAG outputs of the PLD via the three D registers that are clocked by the system clock
(CLK). This clock can be the same clock that the processor uses. Likewise, a read
involves enabling the tri-state buffers and letting the
TDO
signal flow back to the
processor. The design also provides a hardware connection to read back the values in
the
TDI, TMS,
and
TCK
registers. This optional feature is useful during the
development phase, allowing software to check the valid states of the registers in the
interface PLD. In addition, multiplexer logic is included to permit a download cable
to program the device chain. This capability is useful during the prototype phase of
development, when programming must be verified.
Board Layout
The following elements are important when laying out a board that programs via the
IEEE Std. 1149.1 JTAG chain:
■
Treat the
TCK
signal trace as a clock tree
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