9–34
Chapter 9: Using User Flash Memory in MAX II Devices
Software Support for UFM Block
5.
nCS
is pulled back to high to terminate the transmission.
Figure 9–36.
WRSR Operation Sequence
nCS
0
1
2
3
4
5 6 7
8
9 10 11 12 13 14 15
SCK
8-bit
Instruction
SI
MSB
01
H
Status Register In
MSB
SO
High Impendance
Table 9–12.
Block Write Protect Bits for Extended Mode
Status Register Bits
Level
0 (No protection)
3 (Full protection)
BP1
0
1
BP0
0
1
UFM Array Address
Protected
None
000 to 1FF
Table 9–13.
Block Write Protect Bits for Base Mode
Status Register Bits
Level
0 (No protection)
3 (Full protection)
BP1
0
1
BP0
0
1
UFM Array Address
Protected
None
000 to 0FF
ALTUFM SPI Timing Specification
shows the timing specification needed for the SPI Extended mode
(read/write). These
nCS
timing specifications do not apply to the SPI Extended read-
only mode nor any of the SPI Base modes. However, for the SPI Extended mode (read
only) and the SPI Base mode (both read only and read/write), the
nCS
signal and
SCK
are not allowed to toggle at the same time.
shows the timing parameters
which only apply to the SPI Extended mode (read/write).
Figure 9–37.
SPI Timing Waveform
t
HNCSHIGH
nCS
t
SCK2NCS
SCK
t
NCS2SCK
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