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EPM240T100C5N 参数 Datasheet PDF下载

EPM240T100C5N图片预览
型号: EPM240T100C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 可编程逻辑器件输入元件PC
文件页数/大小: 295 页 / 3815 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 9: Using User Flash Memory in MAX II Devices  
9–33  
Software Support for UFM Block  
internal program cycle in the UFM, RDSRis the only valid opcode recognized by the  
interface (therefore, the status register can be read at any time), and nRDYis the only  
valid status bit. Other status bits are frozen and remain unchanged until the internal  
program cycle is ended. RDSRis issued through the following sequence, as shown in  
Figure 9–35:  
1. nCSis pulled low.  
2. Opcode 00000101is transmitted into the interface.  
3. SIignores incoming signals; SOoutput the content of the status register, Bit7  
first and Bit0last.  
4. If nCSis kept low, repeat step 3.  
5. nCSis pulled back to high to terminate the transmission.  
Figure 9–35. RDSR Operation Sequence  
nCS  
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23  
SCK  
SI  
8-bit  
Instruction  
05H  
MSB  
MSB  
High Impendance  
SO  
Status Register Out  
MSB  
MSB  
WRSR (Write Status Register)  
The block protection bits(BP1and BP0) are the status bits used to protect certain  
sections of the UFM from inadvertent write. The BP1and BP0status are updated by  
WRSR. During WRSR, only BP1and BP0in the status register can be written with valid  
information. The rest of the bits in the status register are ignored and not updated.  
When both BP1and BP0are 0, there is no protection for the UFM. When both BP1  
and BP0are 1, there is full protection for the UFM. BP0and BP1are set to 0 upon  
power-up. Table 9–12 describe more on the Block Write Protect Bits for Extended  
mode, while Table 9–13 describes more on the Block Write Protect Bits for Base mode.  
WRSRis issued through the following sequence, as shown in Figure 9–36:  
1. nCSis pulled low.  
2. Opcode 00000001is transmitted into the interface.  
3. An 8-bit status is transmitted into the interface to update BP1and BP0of the status  
register.  
4. If nCSis pulled high too early (before all the eight bits in Step 2 or Step 3 are  
transmitted) or too late (the ninth bit or more is transmitted), WRSRis not executed.  
© October 2008 Altera Corporation  
MAX II Device Handbook