1–6
Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Architecture
Table 1–4. Cyclone III Device Family Speed Grades (Part 2 of 2)
Family
Device
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
E144
—
—
—
—
M164
—
—
—
—
P240
—
—
—
—
F256
—
—
—
—
U256
—
—
—
—
F324
—
—
—
—
F484
U484
F780
C7, C8,
I7
C7, C8,
I7
C7, C8,
I7
C7, C8,
I7
C7, C8, I7 C7, C8, I7
C7, C8, I7 C7, C8, I7
C7, C8, I7
C7, C8, I7
—
—
Cyclone III
LS
lists Cyclone III device family configuration schemes.
Table 1–5. Cyclone III Device Family Configuration Schemes
Configuration Scheme
Active serial (AS)
Active parallel (AP)
Passive serial (PS)
Fast passive parallel (FPP)
Joint Test Action Group (JTAG)
Cyclone III
v
v
v
v
v
Cyclone III LS
v
—
v
v
v
Cyclone III Device Family Architecture
Cyclone III device family includes a customer-defined feature set that is optimized for
portable applications and offers a wide range of density, memory, embedded
multiplier, and I/O options. Cyclone III device family supports numerous external
memory interfaces and I/O protocols that are common in high-volume applications.
The Quartus II software features and parameterizable IP cores make it easier for you
to use the Cyclone III device family interfaces and protocols.
The following sections provide an overview of the Cyclone III device family features.
Logic Elements and Logic Array Blocks
The logic array block (LAB) consists of 16 logic elements and a LAB-wide control
block. An LE is the smallest unit of logic in the Cyclone III device family architecture.
Each LE has four inputs, a four-input look-up table (LUT), a register, and output logic.
The four-input LUT is a function generator that can implement any function with four
variables.
f
For more information about LEs and LABs, refer to the
chapter.
July 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
