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EP3C16Q144C6ES 参数 Datasheet PDF下载

EP3C16Q144C6ES图片预览
型号: EP3C16Q144C6ES
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7308 K
品牌: ALTERA [ ALTERA CORPORATION ]
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5–20
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Hardware Features
Manual Override
If you are using the automatic switchover, you must switch input clocks with the
manual override feature with the
clkswitch
input.
shows an example of a waveform illustrating the switchover feature
when controlled by
clkswitch.
In this case, both clock sources are functional and
inclk0
is selected as the reference clock. A low-to-high transition of the
clkswitch
signal starts the switchover sequence. The
clkswitch
signal must be high for at least
three clock cycles (at least three of the longer clock period if
inclk0
and
inclk1
have
different frequencies). On the falling edge of
inclk0,
the reference clock of the counter,
muxout,
is gated off to prevent any clock glitching. On the falling edge of
inclk1,
the
reference clock multiplexer switches from
inclk0
to
inclk1
as the PLL reference. On
the falling edge of
inclk1,
the reference clock multiplexer switches from
inclk0
to
inclk1
as the PLL reference, and the
activeclock
signal changes to indicate which
clock is currently feeding the PLL.
In this mode, the
activeclock
signal mirrors the
clkswitch
signal. As both blocks are
still functional during the manual switch, neither
clkbad
signals go high. Because the
switchover circuit is positive edge-sensitive, the falling edge of the
clkswitch
signal
does not cause the circuit to switch back from
inclk1
to
inclk0.
When the
clkswitch
signal goes high again, the process repeats. The
clkswitch
signal and the automatic
switch only works depending on the availability of the clock that is switched to. If the
clock is unavailable, the state machine waits until the clock is available.
1
If CLKSWITCH = 1, the automatic switchover function is overridden. While the
clkswitch
signal is high, further switchover action is blocked.
Figure 5–16. Clock Switchover Using the clkswitch Control
inclk0
inclk1
muxout
clkswitch
activeclock
clkbad0
clkbad1
Note to
(1) Both
inclk0
and
inclk1
must be running when the
clkswitch
signal goes high to start a manual clock switchover
event.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation