5–22
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Programmable Bandwidth
■
shows how the VCO frequency gradually decreases when the primary
clock is lost and then increases as the VCO locks on to the secondary clock. After
the VCO locks on to the secondary clock, some overshoot can occur (an
over-frequency condition) in the VCO frequency.
Figure 5–17. VCO Switchover Operating Frequency
Primary Clock Stops Running
Frequency Overshoot
Switchover Occurs
VCO Tracks Secondary Clock
ΔF
vco
■
Disable the system during switchover if the system is not tolerant to frequency
variations during the PLL resynchronization period. You can use the
clkbad[0]
and
clkbad[1]
status signals to turn off the PFD (pfdena =
0)
so the VCO
maintains its last frequency. You can also use the switchover state machine to
switch over to the secondary clock. Upon enabling the PFD, output clock enable
signals (clkena) can disable clock outputs during the switchover and
resynchronization period. After the lock indication is stable, the system can
re-enable the output clock or clocks.
Programmable Bandwidth
The PLL bandwidth is the measure of the PLL’s ability to track the input clock and its
associated jitter. Cyclone III device family PLLs provide advanced control of the PLL
bandwidth using the programmable characteristics of the PLL loop, including loop
filter and charge pump. The closed-loop gain 3-dB frequency in the PLL determines
the PLL bandwidth. The bandwidth is approximately the unity gain point for open
loop PLL response.
Phase Shift Implementation
Phase shift is used to implement a robust solution for clock delays in the Cyclone III
device family. Phase shift is implemented with a combination of the VCO phase
output and the counter starting time. The VCO phase output and counter starting
time are the most accurate methods of inserting delays, because they are purely based
on counter settings, which are independent of process, voltage, and temperature.
You can phase shift the output clocks from the Cyclone III device family PLLs in
either:
■
■
Fine resolution using VCO phase taps, or
Coarse resolution using counter starting time
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
