5–18
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Hardware Features
If you use the SignalTap
®
II tool to probe the
locked
signal before the D flip-flop, the
locked
signal goes low only when
areset
is deasserted. If the
areset
signal is not
enabled, the extra logic is not implemented in the ALTPLL megafunction.
f
For more information about the PLL control signals, refer to the
Clock Switchover
The clock switchover feature allows the PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application,
such as a system that turns on the redundant clock if the previous clock stops running.
Your design can automatically perform clock switchover when the clock is no longer
toggling, or based on the user control signal,
clkswitch.
Automatic Clock Switchover
Cyclone III device family PLLs support a fully configurable clock switchover
capability.
When the current reference clock is not present, the clock-sense block automatically
switches to the backup clock for PLL reference. The clock switchover circuit also sends
out three status signals—clkbad[0],
clkbad[1],
and
activeclock—from
the PLL to
implement a custom switchover circuit. You can select a clock source at the backup
clock by connecting it to the
inclk1
port of the PLL in your design.
shows the block diagram of the switchover circuit built into the PLL.
Figure 5–14. Automatic Clock Switchover Circuit
clkbad0
clkbad1
Activeclock
Clock
Sense
Switchover
State
Machine
clksw
clkswitch
(provides manual
switchover support)
inclk0
inclk1
muxout
n
Counter
refclk
fbclk
PFD
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
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