Chapter 12: IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
IEEE Std. 1149.1 BST Operation Control
12–3
Cyclone III device family supports the IEEE Std. 1149.1 (JTAG) instructions as listed in
Table 12–3. IEEE Std. 1149.1 (JTAG) Instructions Supported by Cyclone III Device Family (Part 1 of 2)
JTAG Instruction
Instruction Code
Description
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial data
pattern to be output at the device pins. Also used by the SignalTap
®
II
embedded logic analyzer.
Allows the external circuitry and board-level interconnects to be tested
by forcing a test pattern at the output pins and capturing test results at
the input pins.
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which
allows the BST data to pass synchronously through selected devices to
adjacent devices during normal device operation.
Selects the 32-bit
USERCODE
register and places it between the
TDI
and
TDO
pins, allowing the
USERCODE
to be serially shifted out of
TDO.
Selects the
IDCODE
register and places it between
TDI
and
TDO,
allowing the
IDCODE
to be serially shifted out of
TDO. IDCODE
is the
default instruction at power up and in
TAP RESET
state.
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which
allows the BST data to pass synchronously through selected devices to
adjacent devices during normal device operation, while tri-stating all of
the I/O pins.
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which
allows the BST data to pass synchronously through selected devices to
adjacent devices during normal device operation while holding I/O pins
to a state defined by the data in the boundary scan register.
Used when configuring Cyclone III device family using the JTAG port
with a USB-Blaster
™
ByteBlaster
™
II, MasterBlaster
™
or ByteBlasterMV
™
download cable, or when using a Jam File, or JBC File via an embedded
processor.
Emulates pulsing the
nCONFIG
pin low to trigger reconfiguration even
though the physical pin is unaffected.
Allows I/O reconfiguration through JTAG ports using the
IOCSR
for
JTAG testing. This is executed after or during configurations.
nSTATUS
pin must go high before you can issue the
CONFIG_IO
instruction.
Allows
CLKUSR
pin signal to replace the internal oscillator as the
configuration clock source.
Allows you to revert the configuration clock source from
CLKUSR
pin
signal set by
EN_ACTIVE_CLK
back to the internal oscillator.
Places the active configuration mode controllers into idle state prior to
CONFIG_IO
to configure the
IOCSR
or perform board level testing.
This instruction might be used in AS and AP configuration schemes to
re-engage the active controller.
Places the 22-bit active boot address register between the
TDI
and
TDO
pins, allowing a new active boot address to be serially shifted into
TDI
and into the active parallel (AP) flash controller. In remote system
upgrade, the
PFC_BOOT_ADDR
instruction sets the boot address for the
factory configuration.
SAMPLE/PRELOAD
00 0000 0101
EXTEST
00 0000 1111
BYPASS
11 1111 1111
USERCODE
00 0000 0111
IDCODE
00 000 0110
HIGHZ
00 0000 1011
CLAMP
00 0000 1010
ICR Instructions
—
PULSE_NCONFIG
00 0000 0001
CONFIG_IO
00 0000 1101
EN_ACTIVE_CLK
01 1110 1110
10 1110 1110
DIS_ACTIVE_CLK
ACTIVE_DISENGAGE
ACTIVE_ENGAGE
10 1101 0000
10 1011 0000
APFC_BOOT_ADDR
10 0111 0000
December 2011
Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
