12–6
Chapter 12: IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
Guidelines for IEEE Std. 1149.1 BST
shows the JTAG chain of mixed voltages and how a level shifter is
inserted in the chain.
Figure 12–1. JTAG Chain of Mixed Voltages
Must be
3.3 V
tolerant
TDI
3.3 V
V
CCIO
2.5 V
V
CCIO
Tester
TDO
Level
Shifter
1.5 V
V
CCIO
1.8 V
V
CCIO
Shift TDO to
level accepted by
tester if necessary
Must be
1.8 V
tolerant
Must be
2.5 V
tolerant
Guidelines for IEEE Std. 1149.1 BST
Use the following guidelines when performing BST with IEEE Std. 1149.1 devices:
■
If the 10 bit checkerboard pattern (1010101010) does not shift out of the instruction
register via the
TDO
pin during the first clock cycle of the
SHIFT_IR
state, the TAP
controller did not reach the proper state. To solve this problem, try one of the
following procedures:
■
Verify that the TAP controller has reached the
SHIFT_IR
state correctly. To
advance the TAP controller to the
SHIFT_IR
state, return to the
RESET
state and
send the code
01100
to the
TMS
pin.
Check the connections to the
VCC, GND, JTAG,
and dedicated configuration pins
on the device.
■
■
Perform a
SAMPLE/PRELOAD
test cycle prior to the first
EXTEST
test cycle to ensure
that known data is present at the device pins when you enter the
EXTEST
mode. If
the
OEJ
update register contains a 0, the data in the
OUTJ
update register is driven
out. The state must be known and correct to avoid contention with other devices in
the system.
Do not perform
EXTEST
testing during ICR. This instruction is supported before or
after ICR, but not during ICR. Use the
CONFIG_IO
instruction to interrupt
configuration and then perform testing, or wait for configuration to complete.
If testing is performed before configuration, hold the
nCONFIG
pin low.
■
■
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
