12. IEEE 1149.1 (JTAG) Boundary-Scan
Testing for the Cyclone III Device Family
December 2011
CIII51014-2.3
CIII51014-2.3
This chapter provides guidelines on using the IEEE Std. 1149.1 boundary-scan test
(BST) circuitry in Cyclone
®
III device family (Cyclone III and Cyclone III LS devices).
BST architecture tests pin connections without using physical test probes, and
captures functional data while a device is operating normally. Boundary-scan cells
(BSCs) in a device can force signals onto pins or capture data from pin or logic array
signals. Forced test data is serially shifted into the boundary-scan cells. Captured data
is serially shifted out and externally compared to expected results.
This chapter contains the following sections:
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IEEE Std. 1149.1 BST Architecture
Cyclone III device family operating in the IEEE Std. 1149.1 BST mode use four
required pins:
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TDI
TDO
TMS
TCK
The
TCK
pin has an internal weak pull-down resistor, while the
TDI
and
TMS
pins have
weak internal pull-up resistors. The
TDO
output pin and all the JTAG input pins are
powered by the V
CCIO
supply of bank 1A. All user I/O pins are tri-stated during JTAG
configuration.
1
For recommendations on how to connect a JTAG chain with multiple voltages across
the devices in the chain, refer to
f
For more information about the description and functionality of all JTAG pins,
registers used by the IEEE Std. 1149.1 BST circuitry, and the test access port (TAP)
controller, refer to
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Cyclone III Device Handbook
Volume 1
December 2011
ALTERA [ ALTERA CORPORATION ]
