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EP2S90F1020C4N 参数 Datasheet PDF下载

EP2S90F1020C4N图片预览
型号: EP2S90F1020C4N
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix II系列提供了以下功能 [The Stratix II family offers the following features]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 238 页 / 2897 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix II Architecture  
Each I/O bank has its own VCCIOpins. A single device can support  
1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different  
VCCIO level independently. Each bank also has dedicated VREFpins to  
support the voltage-referenced standards (such as SSTL-2). The PLL  
banks utilize the adjacent VREFgroup when voltage-referenced  
standards are implemented. For example, if an SSTL input is  
implemented in PLL bank 10, the voltage level at VREFB7is the reference  
voltage level for the SSTL input.  
I/O pins that reside in PLL banks 9 through 12 are powered by the  
VCC_PLL<5, 6, 11, or 12>_OUTpins, respectively. The EP2S60F484,  
EP2S60F780, EP2S90H484, EP2S90F780, and EP2S130F780 devices do not  
support PLLs 11 and 12. Therefore, any I/O pins that reside in bank 11 are  
powered by the VCCIO3pin, and any I/O pins that reside in bank 12 are  
powered by the VCCIO8pin.  
Each I/O bank can support multiple standards with the same VCCIO for  
input and output pins. Each bank can support one VREF voltage level. For  
example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, and  
3.3-V PCI for inputs and outputs.  
On-Chip Termination  
Stratix II devices provide differential (for the LVDS or HyperTransport  
technology I/O standard), series, and parallel on-chip termination to  
reduce reflections and maintain signal integrity. On-chip termination  
simplifies board design by minimizing the number of external  
termination resistors required. Termination can be placed inside the  
package, eliminating small stubs that can still lead to reflections.  
Stratix II devices provide four types of termination:  
Differential termination (RD)  
Series termination (RS) without calibration  
Series termination (RS) with calibration  
Parallel termination (RT) with calibration  
Altera Corporation  
May 2007  
2–89  
Stratix II Device Handbook, Volume 1  
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