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EP2S90F1020C4N 参数 Datasheet PDF下载

EP2S90F1020C4N图片预览
型号: EP2S90F1020C4N
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix II系列提供了以下功能 [The Stratix II family offers the following features]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 238 页 / 2897 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix II Architecture  
The bus-hold circuitry also pulls undriven pins away from the input  
threshold voltage where noise can cause unintended high-frequency  
switching. You can select this feature individually for each I/O pin. The  
bus-hold output drives no higher than VCCIO to prevent overdriving  
signals. If the bus-hold feature is enabled, the programmable pull-up  
option cannot be used. Disable the bus-hold feature when the I/O pin has  
been configured for differential signals.  
The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of  
approximately 7 kΩto weakly pull the signal level to the last-driven state.  
See the DC & Switching Characteristics chapter in the Stratix II Device  
Handbook, Volume 1, for the specific sustaining current driven through this  
resistor and overdrive current used to identify the next-driven input  
level. This information is provided for each VCCIO voltage level.  
The bus-hold circuitry is active only after configuration. When going into  
user mode, the bus-hold circuit captures the value on the pin present at  
the end of configuration.  
Programmable Pull-Up Resistor  
Each Stratix II device I/O pin provides an optional programmable  
pull-up resistor during user mode. If you enable this feature for an I/O  
pin, the pull-up resistor (typically 25 kΩ) weakly holds the output to the  
VCCIO level of the output pin’s bank.  
Programmable pull-up resistors are only supported on user I/O pins, and  
are not supported on dedicated configuration pins, JTAG pins or  
dedicated clock pins.  
Advanced I/O Standard Support  
Stratix II device IOEs support the following I/O standards:  
3.3-V LVTTL/LVCMOS  
2.5-V LVTTL/LVCMOS  
1.8-V LVTTL/LVCMOS  
1.5-V LVCMOS  
3.3-V PCI  
3.3-V PCI-X mode 1  
LVDS  
LVPECL (on input and output clocks only)  
HyperTransport technology  
Differential 1.5-V HSTL Class I and II  
Differential 1.8-V HSTL Class I and II  
Differential SSTL-18 Class I and II  
Differential SSTL-2 Class I and II  
Altera Corporation  
May 2007  
2–85  
Stratix II Device Handbook, Volume 1  
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