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EP2S90F1020C4N 参数 Datasheet PDF下载

EP2S90F1020C4N图片预览
型号: EP2S90F1020C4N
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix II系列提供了以下功能 [The Stratix II family offers the following features]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 238 页 / 2897 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix II Architecture  
Table 2–17. On-Chip Termination Support by I/O Banks (Part 2 of 2)  
On-Chip Termination Support  
I/O Standard Support  
Top & Bottom Banks  
Left & Right Banks  
Series termination with  
calibration  
3.3-V LVTTL  
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
3.3-V LVCMOS  
2.5-V LVTTL  
2.5-V LVCMOS  
1.8-V LVTTL  
1.8-V LVCMOS  
1.5-V LVTTL  
1.5-V LVCMOS  
SSTL-2 Class I and II  
SSTL-18 Class I and II  
1.8-V HSTL Class I  
1.8-V HSTL Class II  
1.5-V HSTL Class I  
1.2-V HSTL  
Parallel termination with  
calibration  
SSTL-2 Class I and II  
SSTL-18 Class I and II  
1.8-V HSTL Class I  
1.8-V HSTL Class II  
1.5-V HSTL Class I and II  
1.2-V HSTL  
LVDS  
Differential termination (1)  
v
v
HyperTransport technology  
Note to Table 2–17:  
(1) Clock pins CLK1, CLK3, CLK9, CLK11, and pins FPLL[7..10]CLKdo not support differential on-chip  
termination. Clock pins CLK0, CLK2, CLK8, and CLK10do support differential on-chip termination. Clock pins in  
the top and bottom banks (CLK[4..7, 12..15]) do not support differential on-chip termination.  
Altera Corporation  
May 2007  
2–91  
Stratix II Device Handbook, Volume 1  
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