TriMatrix Memory
Figure 2–22. M4K RAM Block LAB Row Interface
C4 Interconnect
R4 Interconnect
16
Direct link
Direct link
interconnect
to adjacent LAB
interconnect
to adjacent LAB
36
dataout
M4K RAM
Block
Direct link
Direct link
interconnect
interconnect
from adjacent LAB
from adjacent LAB
datain
byte
enable
control
signals
clocks
address
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
■
■
■
■
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
You cannot use an initialization file to initialize the contents of an M-RAM
block. All M-RAM block contents power up to an undefined value. Only
synchronous operation is supported in the M-RAM block, so all inputs
are registered. Output registers can be bypassed.
2–34
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
ALTERA [ ALTERA CORPORATION ]
