TriMatrix Memory
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful
for implementing small FIFO buffers, DSP, and clock domain transfer
applications. Each block contains 576 RAM bits (including parity bits).
M512 RAM blocks can be configured in the following modes:
■
■
■
■
■
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
1
Violating the setup or hold time on the memory block address
registers could corrupt memory contents. This applies to both
read and write operations.
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
M512 RAM blocks can have different clocks on its inputs and outputs.
The wren, datain, and write address registers are all clocked together
from one of the two clocks feeding the block. The read address, rden, and
output registers can be clocked by either of the two clocks driving the
block. This allows the RAM block to operate in read/write or
input/output clock modes. Only the output register can be bypassed. The
six labclksignals or local interconnect can drive the inclock,
outclock, wren, rden, and outclrsignals. Because of the advanced
interconnect between the LAB and M512 RAM blocks, ALMs can also
control the wrenand rdensignals and the RAM clock, clock enable, and
asynchronous clear signals. Figure 2–19 shows the M512 RAM block
control signal generation logic.
The RAM blocks in Stratix II devices have local interconnects to allow
ALMs and interconnects to drive into RAM blocks. The M512 RAM block
local interconnect is driven by the R4, C4, and direct link interconnects
from adjacent LABs. The M512 RAM blocks can communicate with LABs
on either the left or right side through these row interconnects or with
LAB columns on the left or right side with the column interconnects. The
M512 RAM block has up to 16 direct link input connections from the left
adjacent LABs and another 16 from the right adjacent LAB. M512 RAM
outputs can also connect to left and right LABs through direct link
interconnect. The M512 RAM block has equal opportunity for access and
performance to and from LABs on either its left or right side. Figure 2–20
shows the M512 RAM block to logic array interface.
2–30
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
ALTERA [ ALTERA CORPORATION ]
