PLL Timing Specifications
Table 5–92. Enhanced PLL Specifications (Part 2 of 2)
Name
Description
Min
Typ
Max
Unit
tLOCK
Time required for the
PLL to lock from the
time it is enabled or
the end of device
configuration
0.03
1
ms
tDLOCK
Time required for the
PLL to lock
1
ms
dynamically after
automatic clock
switchover between
two identical clock
frequencies
fSWITCHOVER
Frequency range
where the clock
switchover performs
properly
4
500
MHz
fCLBW
fVCO
PLL closed-loop
bandwidth
0.13
300
1.20
16.90
1,040
MHz
MHz
PLL VCO operating
range for –3 and –4
speed grade devices
PLL VCO operating
range for –5 speed
grade devices
300
840
MHz
fSS
Spread-spectrum
modulation frequency
100
0.4
500
0.6
kHz
%
% spread
Percent down spread
for a given clock
frequency
0.5
tPLL_PSERR
tARESET
Accuracy of PLL
phase shift
15
ps
ns
ns
Minimum pulse width
on aresetsignal.
10
tARESET_RECONFIG Minimum pulse width
on the aresetsignal
when using PLL
500
reconfiguration. Reset
the PLL after
scandonegoes
high.
Notes to Table 5–92:
(1) Limited by I/O fMA X. See Table 5–78 on page 5–69 for the maximum. Cannot exceed fOUT specification.
(2) If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
5–92
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
