DC & Switching Characteristics
Tables 5–92 and 5–93 describe the Stratix II PLL specifications when
operating in both the commercial junction temperature range (0 to 85 °C)
and the industrial junction temperature range (–40 to 100 °C).
PLL Timing
Specifications
Table 5–92. Enhanced PLL Specifications (Part 1 of 2)
Name
Description
Min
2
Typ
Max
500
420
Unit
MHz
MHz
fIN
Input clock frequency
fINPFD
Input frequency to the
PFD
2
fINDUTY
Input clock duty cycle
40
40
60
60
%
%
fEINDUTY
External feedback
input clock duty cycle
tINJITTER
Input or external
feedback clock input
jitter tolerance in
terms of period jitter.
Bandwidth ≤0.85 MHz
0.5
1.0
ns (p-p)
Input or external
feedback clock input
jitter tolerance in
terms of period jitter.
Bandwidth >
ns (p-p)
0.85 MHz
tOUTJITTER
tFCOMP
fOUT
Dedicated clock
output period jitter
ps or mUI
(p-p)
250 ps for ≥ 100 MHz outclk
25 mUI for < 100 MHz outclk
External feedback
compensation time
10
ns
Output frequency for
internal global or
regional clock
1.5
(2)
550.0
MHz
tOUTDUTY
Duty cycle for external
clock output (when set
to 50%).
45
50
55
%
fSCANCLK
Scanclk frequency
100
MHz
ns
tCONFIGPLL
Time required to
reconfigure scan
chains for enhanced
PLLs
174/fSCANCLK
fOUT_EXT
PLL external clock
output frequency
1.5
(2)
550.0 (1)
MHz
Altera Corporation
May 2007
5–91
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
