Timing Model
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 4 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
Drive
Strength
I/O Standard
Column I/O Pins
Row I/O Pins
-4
Dedicated Clock Outputs
-3
-4
-5
-3
-5
-3
-4
-5
Differential
SSTL-18 Class I
(3)
4 mA
6 mA
458
305
225
167
129
173
150
120
109
245
164
123
110
97
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
99
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
99
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
505
336
248
190
148
155
140
110
94
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
99
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
99
8 mA
10 mA
12 mA
8 mA
Differential
SSTL-18 Class II
(3)
16 mA
18 mA
20 mA
4 mA
1.8-V Differential
HSTL Class I (3)
229
153
114
108
104
99
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
4 mA
1.8-V Differential
HSTL Class II (3)
101
98
93
93
88
1.5-V Differential
HSTL Class I (3)
168
112
84
196
131
99
196
131
99
188
125
95
196
131
99
196
131
99
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
87
98
98
90
98
98
86
98
98
87
98
98
1.5-V Differential
HSTL Class II (3)
95
101
100
101
177
177
-
101
100
101
177
177
-
96
101
100
101
177
177
134
101
100
101
177
177
134
95
101
104
143
143
134
94
3.3-V PCI
3.3-V PCI-X
LVDS
134
134
-
155 (1)
155 (1)
-
155
(1)
155
(1)
HyperTransport
technology
-
-
-
-
-
-
155
(1)
155
(1)
-
-
-
LVPECL (4)
-
-
134
134
134
5–76
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
