DC & Switching Characteristics
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
Table 5–33. Stratix II Device Timing Model Status
Device
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
Preliminary
Final
v
v
v
v
v
v
I/O Timing Measurement Methodology
Altera characterizes timing delays at the worst-case process, minimum
voltage, and maximum temperature for input register setup time (tSU
)
and hold time (tH). The Quartus II software uses the following equations
to calculate tSU and tH timing for Stratix II devices input signals.
tSU = + data delay from input pin to input register
+ micro setup time of the input register
– clock delay from input pin to input register
tH = – data delay from input pin to input register
+ micro hold time of the input register
+ clock delay from input pin to input register
Figure 5–3 shows the setup and hold timing diagram for input registers.
Altera Corporation
May 2007
5–21
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
