DC & Switching Characteristics
Table 5–31. Series & Differential On-Chip Termination Specification for Left & Right I/O Banks
Resistance Tolerance
Commercial Industrial
Symbol
Description
Conditions
Unit
Max
Max
25-Ω RS
3.3/2.5
Internal series termination without
calibration (25-Ω setting)
VCCIO = 3.3/2.5 V
VCCIO = 3.3/2.5/1.8 V
VCCIO = 1.5 V
30
30
%
50-Ω RS
3.3/2.5/1.8
Internal series termination without
calibration (50-Ω setting)
30
36
20
30
36
25
%
%
%
50-Ω RS 1.5 Internal series termination without
calibration (50-Ω setting)
RD
VCCIO = 2.5 V
Internal differential termination for
LVDS or HyperTransport technology
(100-Ω setting)
Pin Capacitance
Table 5–32 shows the Stratix II device family pin capacitance.
Table 5–32. Stratix II Device Capacitance
Symbol
Note (1)
Parameter
Typical
5.0
Unit
pF
CIOTB
CIOLR
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
Input capacitance on I/O pins in I/O banks 1, 2, 5, and 6, including high-
speed differential receiver and transmitter pins.
6.1
pF
CCLKTB
6.0
pF
Input capacitance on top/bottom clock input pins: CLK[4..7]and
CLK[12..15].
CCLKLR
6.1
3.3
pF
pF
Input capacitance on left/right clock inputs: CLK0, CLK2, CLK8, CLK10.
CCLKLR+
Input capacitance on left/right clock inputs: CLK1, CLK3, CLK9, and
CLK11.
COUTFB
Input capacitance on dual-purpose clock output/feedback pins in PLL
banks 9, 10, 11, and 12.
6.7
pF
Note to Table 5–32:
(1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within 0.5pF
Altera Corporation
May 2007
5–19
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
