DC & Switching Characteristics
Bus Hold Specifications
Table 5–29 shows the Stratix II device family bus hold specifications.
Table 5–29. Bus Hold Parameters
VCCIO Level
1.8 V
Parameter Conditions
Unit
μA
1.2 V
1.5 V
2.5 V
3.3 V
Min
Max
Min Max Min Max Min
Max Min Max
Low
V
IN > VIL
22.5
25.0
30.0
50.0
70.0
sustaining
current
(maximum)
High
V
IN < VIH
–22.5
–25.0
–30.0
–50.0
–70.0
μA
sustaining
current
(minimum)
Low
overdrive
current
0 V < VIN
VCCIO
<
120
–120
0.95
160
–160
1.00
200
–200
1.07
300
500
μA
High
overdrive
current
0 V < VIN
VCCIO
<
–300
–500 μA
Bus-hold
trip point
0.45
0.50
0.68
0.70
1.70 0.80 2.00
V
On-Chip Termination Specifications
Tables 5–30 and 5–31 define the specification for internal termination
resistance tolerance when using series or differential on-chip termination.
Table 5–30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 1 of 2)
Notes (1), 2
Resistance Tolerance
Symbol
Description
Conditions
Commercial
Max
Industrial
Max
Unit
25-Ω RS
3.3/2.5
Internal series termination with
calibration (25-Ω setting)
VCCIO = 3.3/2.5 V
5
10
%
Internal series termination without VCCIO = 3.3/2.5 V
30
30
%
calibration (25-Ω setting)
Altera Corporation
May 2007
5–17
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
