Hot Socketing & Power-On Reset
Figure 4–2. Transistor Level Diagram of FPGA Device I/O Buffers
V
Logic Array
Signal
PAD
(1)
(2)
V
CCIO
n+
n+
p+
p+
n-well
n+
p-well
p-substrate
Notes to Figure 4–2:
(1) This is the logic array signal or the larger of either the VCCIO or VPAD signal.
(2) This is the larger of either the VCCIO or VPAD signal.
Stratix II devices have a POR circuit to keep the whole device system in
reset state until the power supply voltage levels have stabilized during
power-up. The POR circuit monitors the VCCINT, VCCIO, and VCCPD voltage
levels and tri-states all the user I/O pins while VCC is ramping up until
normal user levels are reached. The POR circuitry also ensures that all
eight I/O bank VCCIO voltages, VCCPD voltage, as well as the logic array
VCCINT voltage, reach an acceptable level before configuration is
triggered. After the Stratix II device enters user mode, the POR circuit
continues to monitor the VCCINT voltage level so that a brown-out
condition during user mode can be detected. If there is a VCCINT voltage
sag below the Stratix II operational level during user mode, the POR
circuit resets the device.
Power-On Reset
Circuitry
When power is applied to a Stratix II device, a power-on-reset event
occurs if VCC reaches the recommended operating range within a certain
period of time (specified as a maximum VCC rise time). The maximum
VCC rise time for Stratix II device is 100 ms. Stratix II devices provide a
dedicated input pin (PORSEL) to select POR delay times of 12 or 100 ms
during power-up. When the PORSELpin is connected to ground, the POR
time is 100 ms. When the PORSELpin is connected to VCC, the POR time
is 12 ms.
Altera Corporation
May 2007
4–5
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
