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EP2S90F1020C4N 参数 Datasheet PDF下载

EP2S90F1020C4N图片预览
型号: EP2S90F1020C4N
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix II系列提供了以下功能 [The Stratix II family offers the following features]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 238 页 / 2897 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Operating Conditions  
Table 5–2. Maximum Duty Cycles in Voltage Transitions  
Maximum  
Duty Cycles  
Symbol  
Parameter  
Condition  
Unit  
VI  
Maximum duty cycles  
in voltage transitions  
VI = 4.0 V  
VI = 4.1 V  
VI = 4.2 V  
VI = 4.3 V  
VI = 4.4 V  
VI = 4.5 V  
100  
90  
50  
30  
17  
10  
%
%
%
%
%
%
Recommended Operating Conditions  
Table 5–3 contains the Stratix II device family recommended operating  
conditions.  
Table 5–3. Stratix II Device Recommended Operating Conditions (Part 1 of 2)  
Note (1)  
Symbol  
VCCINT  
VCCIO  
Parameter  
Conditions  
Minimum Maximum Unit  
Supply voltage for internal logic  
100 μs risetime 100 ms (3)  
100 μs risetime 100 ms (3), (6)  
1.15  
1.25  
V
V
Supply voltage for input and  
output buffers, 3.3-V operation  
3.135  
(3.00)  
3.465  
(3.60)  
Supply voltage for input and  
output buffers, 2.5-V operation  
100 μs risetime 100 ms (3)  
100 μs risetime 100 ms (3)  
2.375  
2.625  
V
V
V
V
V
Supply voltage for input and  
output buffers, 1.8-V operation  
1.71  
1.89  
Supply voltage for output buffers, 100 μs risetime 100 ms (3)  
1.5-V operation  
1.425  
1.14  
1.575  
1.26  
Supply voltage for input and  
output buffers, 1.2-V operation  
100 μs risetime 100 ms (3)  
VCCPD  
Supply voltage for pre-drivers as 100 μs risetime 100 ms (4)  
well as configuration and JTAG  
3.135  
3.465  
I/O buffers.  
VCCA  
VCCD  
VI  
Analog power supply for PLLs  
Digital power supply for PLLs  
Input voltage (see Table 5–2)  
Output voltage  
100 μs risetime 100 ms (3)  
100 μs risetime 100 ms (3)  
(2), (5)  
1.15  
1.15  
–0.5  
0
1.25  
1.25  
4.0  
V
V
V
V
VO  
VCCIO  
5–2  
Altera Corporation  
May 2007  
Stratix II Device Handbook, Volume 1  
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