欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP2C8T144I8N 参数 Datasheet PDF下载

EP2C8T144I8N图片预览
型号: EP2C8T144I8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 470 页 / 5765 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP2C8T144I8N的Datasheet PDF文件第402页浏览型号EP2C8T144I8N的Datasheet PDF文件第403页浏览型号EP2C8T144I8N的Datasheet PDF文件第404页浏览型号EP2C8T144I8N的Datasheet PDF文件第405页浏览型号EP2C8T144I8N的Datasheet PDF文件第407页浏览型号EP2C8T144I8N的Datasheet PDF文件第408页浏览型号EP2C8T144I8N的Datasheet PDF文件第409页浏览型号EP2C8T144I8N的Datasheet PDF文件第410页  
PS Configuration  
the five common signals (nCONFIG, nSTATUS, DCLK, DATA0, and  
CONF_DONE) between the cable and the configuration device. You can  
also remove the configuration device from the board when configuring  
the FPGA with the cable. Figure 13–21 shows a combination of a  
configuration device and a download cable to configure an FPGA.  
Figure 13–21. PS Configuration with a Download Cable & Configuration Device Circuit  
USB Blaster, ByteBlaster II,  
MasterBlaster, or ByteBlasterMV  
10-Pin Male Header  
V
(1)  
CC  
V
(1)  
CC  
V
CC  
10 kΩ  
(5)  
(Passive Serial Mode)  
10 kΩ  
(5)  
Cyclone II FPGA  
CONF_DONE  
(1)  
V
CC  
Pin 1  
V
CC  
10 kΩ  
(4)  
MSEL0  
nSTATUS  
DCLK  
MSEL1  
GND  
VIO (2)  
nCEO N.C. (6)  
nCE  
GND  
(3)  
(3)  
(3)  
DATA0  
nCONFIG  
GND  
Configuration  
Device  
(3)  
DCLK  
DATA  
OE (5)  
nCS (5)  
(3)  
nINIT_CONF (4)  
Notes to Figure 13–21:  
(1) The pull-up resistor should be connected to the same supply voltage as the configuration device.  
(2) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s  
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV,  
this pin is a no connect. In the USB-Blaster and ByteBlaster II, this pin is connected to nCEwhen it is used for AS  
programming, otherwise it is a no connect.  
(3) You should not attempt configuration with a download cable while a configuration device is connected to a  
Cyclone II device. Instead, you should either remove the configuration device from its socket when using the  
download cable or place a switch on the five common signals between the download cable and the configuration  
device.  
(4) The nINIT_CONFpin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up  
resistor that is always active. This means an external pull-up resistor should not be used on the nINIT_CONFto  
nCONFIGline. The nINIT_CONFpin does not need to be connected if its functionality is not used. If nINIT_CONF  
is not used or not available (e.g., on EPC1 devices), nCONFIGmust be pulled to VCC either directly or through a  
resistor (if reconfiguration is required, a resistor is necessary).  
(5) The enhanced configuration devices’ OEand nCSpins have internal programmable pull-up resistors. If internal  
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors  
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and  
OE pull-ups on configuration device option when generating programming files.  
(6) The nCEOpin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCEpin.  
13–52  
Altera Corporation  
February 2007  
Cyclone II Device Handbook, Volume 1  
 复制成功!