PS Configuration
PS Configuration Using a Download Cable
In PS configuration, an intelligent host (e.g., a PC) can use a download
cable to transfer data from a storage device to the Cyclone II device. You
can use the Altera USB-Blaster universal serial bus (USB) port download
cable, MasterBlaster™ serial/USB communications cable, ByteBlaster II
parallel port download cable, or the ByteBlasterMV™ parallel port as a
download cable.
Upon power up, the Cyclone II device goes through POR, which lasts
approximately 100 ms for non “A” devices. During POR, the device
resets, holds nSTATUSlow, and tri-states all user I/O pins. Once the
FPGA successfully exits POR, the nSTATUSpin is released and all user
I/O pins continue to be tri-stated.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Cyclone II Device
Handbook.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While the nCONFIGor nSTATUSpins are low, the device is
in reset. To initiate configuration in this scheme, the download cable
generates a low-to-high transition on the nCONFIGpin.
1
Make sure VCCINT and VCCIO for the banks where the
configuration and JTAG pins reside are powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIGtransitions high, the Cyclone II device comes out of reset
and begins configuration. The Cyclone II device releases the open-drain
nSTATUSpin, which is then pulled high by an external 10-kΩpull-up
resistor. Once nSTATUStransitions high, the Cyclone II device is ready to
receive configuration data. The programming hardware or download
cable then transmits the configuration data one bit at a time to the
device’s DATA0pin. The configuration data is clocked into the target
device until CONF_DONEgoes high. The CONF_DONEpin must have an
external 10-kΩpull-up resistor in order for the device to initialize.
When using a download cable, you cannot use the Auto-restart
configuration after error option. You must manually restart
configuration in the Quartus II software when an error occurs.
Additionally, you cannot use the Enable user-supplied start-up clock
(CLKUSR) option when programming the FPGA using the Quartus II
programmer and download cable. This option is disabled in the SOF.
Therefore, if you turn on the CLKUSRoption, you do not need to provide
a clock on CLKUSRwhen you are configuring the FPGA with the
13–48
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
ALTERA [ ALTERA CORPORATION ]
