Configuring Cyclone II Devices
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For more information on how to use the USB-Blaster, MasterBlaster,
ByteBlaster II or ByteBlasterMV cables, refer to the following documents:
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USB-Blaster USB Port Download Cable Data Sheet
MasterBlaster Serial/USB Communications Cable Data Sheet
ByteBlaster II Parallel Port Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
The Joint Test Action Group (JTAG) has developed a specification for
boundary-scan testing. This boundary-scan test (BST) architecture allows
you to test components on PCBs with tight lead spacing. The BST
architecture can test pin connections without using physical test probes
and capture functional data while a device is operating normally. The
JTAG circuitry can also be used to shift configuration data into the device.
The Quartus II software automatically generates SOF files that can be
used for JTAG configuration with a download cable in the Quartus II
programmer.
JTAG
Configuration
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For more information on JTAG boundary-scan testing, see the following
documents:
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IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone II Devices
chapter in Volume 2 of the Cyclone II Device Handbook
Jam Programming & Testing Language Specification
Cyclone II devices are designed such that JTAG instructions have
precedence over any device configuration modes. This means that JTAG
configuration can take place without waiting for other configuration
modes to complete. For example, if you attempt JTAG configuration of
Cyclone II devices during PS configuration, PS configuration terminates
and JTAG configuration begins. If the Cyclone II MSELpins are set to AS
or fast AS mode, the Cyclone II device does not output a DCLKsignal
when JTAG configuration takes place.
1
You cannot use the Cyclone II decompression feature if you are
configuring your Cyclone II device when using JTAG-based
configuration.
Altera Corporation
February 2007
13–53
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
