PS Configuration
PS Configuration Timing
A PS configuration must meet the setup and hold timing parameters and
the maximum clock frequency. When using a microprocessor or another
intelligent host to control the PS interface, ensure that you meet these
timing requirements.
Figure 13–12 shows the timing waveform for PS configuration for
Cyclone II devices.
Figure 13–12. PS Configuration Timing Waveform
Note (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
tCLK
CONF_DONE (3)
t
CH tCL
tCF2CD
tST2CK
DCLK (4)
tDH
Bit 2 Bit 3
Bit n
Bit 0 Bit 1
DATA
(5)
tDSU
User I/O Tri-stated with internal pull-up resistor
INIT_DONE
User Mode
tCD2UM
Notes to Figure 13–12:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUSand CONF_DONE
are at logic high levels. When nCONFIGis pulled low, a reconfiguration cycle begins.
(2) Upon power-up, the Cyclone II device holds nSTATUSlow for the time of the POR delay.
(3) Upon power-up, before and during configuration, CONF_DONEis low.
(4) In user mode, drive DCLKeither high or low when using the PS configuration scheme, whichever is more
convenient. When using the AS configuration scheme, DCLKis a Cyclone II output pin and should not be driven
externally.
(5) Do not leave the DATApin floating after configuration. Drive it high or low, whichever is more convenient.
13–30
Altera Corporation
February 2007
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
