Configuring Cyclone II Devices
Reset Stage
When nCONFIGor nSTATUSare low, the device is in reset. After POR, the
Cyclone II device releases nSTATUS. An external 10-kΩpull-up resistor
pulls the nSTATUSsignal high, and the Cyclone II device enters
configuration mode.
1
VCCINT and VCCIO of the banks where the configuration and
JTAG pins reside need to be fully powered to the appropriate
voltage levels in order to begin the configuration process.
Configuration Stage
The serial clock (DCLK) generated by the Cyclone II device controls the
entire configuration cycle and provides the timing for the serial interface.
Cyclone II devices use an internal oscillator to generate DCLK. Using the
MSEL[]pins, you can select either a 20- or 40-MHz oscillator. Although
you can select either 20- or 40-MHz oscillator when designing with serial
configuration devices, the 40-MHz oscillator provides faster
configuration times. There is some variation in the internal oscillator
frequency because of the process, temperature, and voltage conditions in
Cyclone II devices. The internal oscillator is designed such that its
maximum frequency is guaranteed to meet EPCS device specifications.
Table 13–5 shows the AS DCLKoutput frequencies.
Table 13–5. AS DCLK Output Frequency
Note (1)
Typical
Oscillator Selected
Minimum
Maximum
Units
40 MHz
20 MHz
20
10
26
13
40
20
MHz
MHz
Note to Table 13–5:
(1) These values are preliminary.
In both AS and Fast AS configuration schemes, the serial configuration
device latches input and control signals on the rising edge of DCLKand
drives out configuration data on the falling edge. Cyclone II devices drive
out control signals on the falling edge of DCLKand latch configuration
data on the falling edge of DCLK.
In configuration mode, the Cyclone II device enables the serial
configuration device by driving its nCSOoutput pin low, which connects
to the chip select (nCS) pin of the configuration device. The Cyclone II
device uses the serial clock (DCLK) and serial data output (ASDO) pins to
send operation commands and/or read address signals to the serial
Altera Corporation
February 2007
13–9
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
