Configuring Cyclone II Devices
Figure 13–4. Multiple Device AS Configuration
V
V
V
V
CC
(1)
(1)
(1)
(2)
CC
CC
CC
10 kΩ
10 kΩ
10 kΩ
10 kΩ
Serial Configuration
Device
Cyclone II FPGA
Master Device
Cyclone II FPGA
Slave Device
nSTATUS
nSTATUS
CONF_DONE
CONF_DONE
nCEO
(3)
N.C.
nCONFIG
nCE
nCONFIG
nCE
nCEO
V
CC
GND
V
CC
DATA
DATA0
DCLK
nCSO
ASDO
MSEL1
MSEL0
DATA0
DCLK
DCLK
nCS
MSEL1
MSEL0
ASDI
GND
GND
Notes to Figure 13–4:
(1) Connect the pull-up resistors to a 3.3-V supply.
(2) Connect the pull-up resistor to the VCCIO supply voltage of I/O bank that the nCEOpin resides in.
(3) The nCEOpin can be left unconnected or used as a user I/O pin when it does not feed another device’s nCEpin.
As shown in Figure 13–4, the nSTATUSand CONF_DONEpins on all target
FPGAs are connected together with external pull-up resistors. These pins
are open-drain bidirectional pins on the FPGAs. When the first device
asserts nCEO(after receiving all of its configuration data), it releases its
CONF_DONEpin. However, the subsequent devices in the chain keep the
CONF_DONEsignal low until they receive their configuration data. When
all the target FPGAs in the chain have received their configuration data
and have released CONF_DONE, the pull-up resistor pulls this signal high,
and all devices simultaneously enter initialization mode.
Altera Corporation
February 2007
13–13
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
